Electronic packages typically incorporate a plurality of surface mount electronic devices, such as flip chips, ball grid arrays, and circuit components such as diodes, inductors, capacitors, resistors, varisters, etc., assembled onto a printed circuit board. The printed circuit board typically includes a dielectric substrate (e.g., organic resin reinforced by fibers) and multiple layers of electrically conductive circuit traces. Many electronic packages employ lead-less surface mount devices that are connected to the printed circuit board via solder joints (e.g., solder bumps).
Many conventional soldered surface mount devices have been known to suffer from thermal fatigue in the solder joint, particularly when large surface mount devices are mounted on an organic circuit board and utilized in an environment experiencing high temperature and/or wide temperature variations. Solder joint fatigue may be caused by large differences in the differential coefficients of thermal expansion (CTE) that often exists between the circuit board and the surface mount device materials. The differences in thermal expansion can result in catastrophic cracking of brittle components such as surface mount capacitors. Generally, larger components experience higher stress and, thus, shorter component life. However, large components are often desirable because fewer components are typically required.
Surface mount devices typically have much smaller coefficients of thermal expansion as compared to organic-based substrates employed in the circuit board. Temperature fluctuations of the electronic package with continuous power cycles generally produce accumulative fatigue in the solder joints. This accumulative thermal fatigue reduces intergranular precipitation and alloy separation in the solder joints that accelerates component breakage. The solder joint fatigue may be further accelerated by the presence of vibrations. Additionally, some surface mount devices are pulled down tightly to the mounting pads by the action of gravity, soldering and capillary attraction, thereby resulting in very low columnar compliance. This may further result in catastrophic electrical failure of the package due to breakage of the solder joint and/or surface mount device.
Several approaches have been proposed to elevate the surface mount device(s) from the circuit board. According to one approach, high temperature standoff members are disposed in the solder paste, such that during reflow the high temperature solder standoff members remain solid (rigid), and thus provide a standoff height to elevate the surface mount device from the circuit board. One example of an approach that employs standoff members in the solder joint is disclosed in U.S. Pat. No. 6,986,454, the entire disclosure of which is hereby incorporated herein by reference.
While the aforementioned approach overcomes some problems and/or drawbacks of prior known solder joint connections, some drawbacks may still exist. Prior known connections may restrict underfill and overmold flow materials that may be required to make some components more reliable during thermal cycling. Additionally, the ability of prior conventional approaches to maintain solder joint thickness may be limited by solder stop and solder mask pattern registration.
Accordingly, it is therefore desirable to provide for an electronic package having a surface mount device to circuit board interconnection that does not unduly suffer adverse thermal fatigue. In particular, it is desirable to provide for an electronic package that eases restrictions to underfill and overmold flow materials and does not unduly limit the ability to maintain solder joint thickness by solder stop and solder mask pattern registration.